CONTROL REGISTER

A tiny MMU for controlling the paged portion of RAM and the placement of the custom chip RAM, as well as an output LED and an input button. The computer offers a memory map which always begins with some unpaged SRAM (memory which is unaffected by the MMU). The stack should be placed at the end of this region. The interrupt vectors and initial program counter all reside at the beginning of this region. The portions of the main program, as well as bank-switching code, should/could also reside here. The size of this unpaged memory, is controlled by the S value in this register. Following the unpaged memory, is (possibly) a region of paged RAM, which will be discussed shortly. Following the paged RAM, is the custom chip RAM (Audio & Video). The content of these memory regions, depends upon the configuration of the specific chip. Following the custom chip memory, is (possibly) a region of paged RAM. Basically, the paged RAM shows through wherever there is not something else. The paged RAM can be manipulated using a variety of bits in this register, which can ultimately expose the entire 128K of SRAM through the available window. NOTE that you can (accidentally or intentionally) configure the MMU to mirror the unpaged memory to another region of the memory map. The unpaged memory always lies at the very beginning of SRAM.

u8 in IO at 0x00 called CONTROLREG

const SRAM_BANK_0

const SRAM_BANK_1

const SRAM_BANK_2

const SRAM_BANK_3

const SRAM_BANK_4

const SRAM_BANK_5

const SRAM_BANK_6

const SRAM_BANK_7

const LED_OFF

const LED_ON

const LED_BIT

const LED_MASK

const SRAM_UNPAGED_SIZE_0K

const SRAM_UNPAGED_SIZE_8K

const SRAM_UNPAGED_SIZE_16K

const SRAM_UNPAGED_SIZE_24K

const SRAM_UNPAGED_SIZE_32K

const SRAM_UNPAGED_SIZE_40K

const SRAM_UNPAGED_SIZE_48K

const SRAM_UNPAGED_SIZE_56K

const BUTTON_MASK

const BUTTON_BIT

const BUTTON_DOWN

const BUTTON_UP