Controls the state of the timer
u8 in RAM at 0xE1A0 called TIMER0_CONTROL
u8 in RAM at 0xE1A4 called TIMER1_CONTROL
u8 in RAM at 0xE1A8 called TIMER2_CONTROL
u8 in RAM at 0xE1AC called TIMER3_CONTROL
76543210
ExxxxxxA
E = RW 1 = Enable Timer (allow the timer to count), 0 = Disable Timer (stop the counter)
A = RW AutoRestart flag.
If set, the timer will restart from the specified count, after reaching 0.
If clear, the timer will clear its' own enable flag once it reaches 0.
The timer is made up of two parts. A prescaler, which produces a lower frequency from the internal 62Mhz frequency, and a counter, which then divides that lower frequency to produce the intended time delay.
This prescaler is used to divide-down the internal VideoChip clock, to something more useful to the counter side of the timer.
The prescaler can divide the 62Mhz internal clock by a variety of values, to produce new frequencies that the counter then counts.
SCALED_FREQ = 62Mhz / (((PRESCALE*256)+63)+1)
u8 in RAM at 0xE1A1 called TIMER0_PRESCALE
u8 in RAM at 0xE1A5 called TIMER1_PRESCALE
u8 in RAM at 0xE1A9 called TIMER2_PRESCALE
u8 in RAM at 0xE1AD called TIMER3_PRESCALE
76543210
PPPPPPPP
P = RW The PRESCALE value as shown in the above equation.
This counter is used to divide-down the prescaled clock (SCALED_FREQ), to produce the target frequency.
The counter can divide the SCALED_FREQ clock by a wide variety of values, to produce a large range of target frequencies.
TARGET_FREQ = SCALED_FREQ / (((COUNTH*256)+COUNTL)+1)
This timer will expire (and set its' interrupt request flag, and potentially auto-restart) at TARGET_FREQ.
NOTE: When writing the count, you MUST first write the low byte, then write the high byte. Internally, the hardware latches the low byte into a temporary location, while awaiting the high byte. When it recieves the high byte, it then writes the complete value (both halves) into the hardware counter as a single operation. Writing a new count, will cause an enabled timer to reload the new count immediately, and continue counting. A disabled timer will also be loaded with a new count, but must still be enabled before counting will begin.
NOTE: When reading the count, you MUST first read the low byte, then read the high byte. Internally, the hardware latches the high byte into a temporary location, when the low byte is read. When the high byte is read, you are actually reading the latched value. This system guarantees that you read a valid number every time.
u8 in RAM at 0xE1A2 called TIMER0_COUNTERL
u8 in RAM at 0xE1A6 called TIMER1_COUNTERL
u8 in RAM at 0xE1AA called TIMER2_COUNTERL
u8 in RAM at 0xE1AE called TIMER3_COUNTERL
111111
5432109876543210
HHHHHHHHLLLLLLLL
L = RW The low byte of the count value.
H = RW The high byte of the count value.
u8 in RAM at 0xE1A3 called TIMER0_COUNTERH
u8 in RAM at 0xE1A7 called TIMER1_COUNTERH
u8 in RAM at 0xE1AB called TIMER2_COUNTERH
u8 in RAM at 0xE1AF called TIMER3_COUNTERH