Controls which interrupt sources can actually interrupt the CPU when a flag gets set in the INTREQUEST register.
NOTE: Once an interrupt has been deemed necessary, the /INT line becomes active, which ultimately causes an interrupt in the CPU. This /INT line will remain active until the appropriate INTREQUEST bit has been cleared. Failing to clear the necessary INTREQUEST bits before exiting the ISR routine, will mean that another interrupt will immediately be triggered.
u8 in IO at 0x82 called INTENABLE
76543210
MVKxDCBA
M = RW Master Interrupt Enable. Clearing this bit, disables all interrupts.
V = RW VBlank Interrupt Enable
K = RW Copper Interrupt Enable
D = RW Timer3 Interrupt Enable
C = RW Timer2 Interrupt Enable
B = RW Timer1 Interrupt Enable
A = RW Timer0 Interrupt Enable
Read: Indicates which interrupt sources are currently making a request to be serviced. Note that a request to be serviced MAY cause a physical interrupt to occur, but that depends upon the configuration of the INTENABLE register.
Write: Writing a 1 to any bit(s) in this register, causes those request flags to be cleared.
u8 in IO at 0x83 called INTREQUEST
76543210
xVKxDCBA
V = RW 1 = VBlank interrupt has been requested.
K = RW 1 = Copper interrupt has been requested.
D = RW 1 = Timer3 interrupt has been requested.
C = RW 1 = Timer2 interrupt has been requested.
B = RW 1 = Timer1 interrupt has been requested.
A = RW 1 = Timer0 interrupt has been requested.
| Name | Value | Comment |
| IF_MasterEnable | 128 | |
| IF_Vblank | 64 | |
| IF_Copper | 32 | |
| IF_Timer3 | 8 | |
| IF_Timer2 | 4 | |
| IF_Timer1 | 2 | |
| IF_Timer0 | 1 |